Tutorial and Panel Updates

The date and tentative time has been announced for the tutorial Properties and Applications of Carbon Nanotubes and Other 1D Nanostructures held by Dr. Wei Liu. It will be held on Sunday September 14, 2008 from 8:30am - 12pm unless there are future changes. See details at http://www.nanonets.org/tutorial.shtml.

An additional member has been confirmed for the "Using Advanced Micro/Nano-electronic Technology to Establish Neuromorphic Systems" panel chaired by Dr. Wei Wang. The newest addition to the panel is Dr. Shih-Chii Liu, Institute of Neuroinformatics, Zurich, Switzerland. Please see http://www.nanonets.org/panel.shtml for more details.

~Damira (Nano-Net 2008 Webmaster)

Wei Wang - Panel Chair and Panel

We are pleased to announce Wei Wang as Panel Chair for Nano-Net 2008. Dr. Wang is an Assistant Professor and Senior Research Scientist of Nanoscale Engineering with a Ph.D., in Electrical and Computer Engineering from Concordia University, Montreal, Canada and a B.S., in Electrical and Computer Engineering from Beijing University of Aeronautics, Beijing, China. His main research areas include: modeling and simulation of nanoscale devices and interconnects, CMOS-nano hybrid circuits, 3D IC, FPGA and ASIC design.

The panel he will chair is titled, "Using Advanced Micro/Nano-electronic Technology to Establish Neuromorphic Systems Panel" and will include among others, Prof. Grarrett Rose, ECE Department of Polytech University; Dr. Vladimir Gorelik, Founder of Neuronix; Prof. Masud Chowdhury, ECE Department, University of Illinois at Chicago; and Dr. Mathew Hynd, Wadsworth, Albany, NY. Other panelists will be announced as they are confirmed.

To start the panel, several questions will be raised regarding the challenges of designing and building devices, circuits, and systems for neuromorphic applications. Then, each panelist will speak for 10-20 minutes about their perspectives to these challenges. Then, the audiences can ask questions to the panel.

Some of the questions asked will be:

In the device level, what is current research status using the CMOS-related technology (analog or mixed signal) to build neuromorphic systems? What are the main challenges? Can CMOS-nano hybrid approach really be an efficient and feasible approach and show improvement over the CMOS-based neuromorphic systems? Some panelists are using CMOS, some are using nanodevices. They will have different perspectives.

In the circuit level, should we use simplified synapses/neurons (digital multivalue) or complicated analog circuitries? Some panelists are suggesting to use complicated synapses/neurons that really mimick the human system (analog) but are difficult to build. Some panelists are using a binary or mutlivalue digital circuit to build a simplified synapse/neuron.

The panel can discuss these different approaches.

In the system and architecture level, what is the impact of the model, algorithm and architecture of the neuromorphic system impact to the hardware development? Since the real human cortex is a 3D structure, is it necessary to use 3D IC architecture to build such systems?

Wei Wang - New TPC Member

We are pleased to annouce our new Technical Program Committee member, Wei Wang from the University at Albany, State University of New York College of Nanoscale Science and Engineering. He received his PhD in Electrical and Computer Engineering from Concordia University in Montreal, Canada in 2002 and is currently an Assistant Professor.

His research interests include modeling and simulation of nanoscale devices and interconnects, CMOS-nano hybrid circuits, 3D IC, FPGA and ASIC design, and computer arithmetic and cryptography. Dr. Wang has over 90 journal and conference publications and two US patents. He is an editor of Journal of Computer Science and Technology and Journal of Computers and was a Section Chair of IWSOC04 and SPND 2004 conferences and also served at the technical committee of IEEE IWSOC 04, Great Lake VLSI 2005, 2007, ISCAS 2007, 2008 and NanoArch 2008 conferences.

Dr. Wang is also a member of IEEE. He is a technical committee (TC) member of IEEE Nano and Giga TC and IEEE VLSI System Design TC. He served as a panelist for NSF NIRT program. He was the executive committee member of IEEE Central Indiana Section and helped organize IEEE Indiana Workshop in June 2006.

~Damira (Nano-Net Webmaster)